The present invention relates generally to the testing of timing jitter, and in particular, to an apparatus and method for providing a programmable jitter signal generator. Timing jitter is defined as the short-term deviation in significant instants of digital signals as referenced to their equidistant normal instants.
As shown in FIG. 1, an exemplary plot of jitter is indicated generally by the reference numeral 100. The solid square wave 110 represents a jitter-free reference signal where the rising edges and falling edges are equally distant from each other. The dashed square waves 112 and 114 are signals with early transition and late transition jitter, respectively. By comparing the timing instant of the rising edges or falling edges between these signals and the reference signal 110, it can be seen there are timing deviations. These timing deviations are called timing jitter.
In today's high-speed computing and communications systems, jitter is a crucial parameter. It is important for such systems to minimize the impact from the timing jitter, and to tolerate a certain level of timing jitter in the input signal while maintaining performance. Accordingly, high-speed computing and communications system must be tested for their tolerance to jitter.
Turning to FIG. 2, a test setup for testing system jitter tolerance ability is indicated generally by the reference numeral 200. The setup 200 includes three blocks, a jitter signal generator 210, a system under test 212 in signal communication with the generator 210, and a system response analyzer 214 in signal communication with the system 212.
In operation of a test, the jitter signal generator 210 generates a signal with known jitter and applies it to the system under test 212. The output of the system under test is its response to the input with jitter. This response is passed into the system response analyzer block 214, where the system jitter tolerance is evaluated.
To conduct the jitter tolerance test, the type of jitter signal generator used is of paramount importance. It should be able to generate jitter in a controllable fashion and then deliberately inject the jitter into the data stream. A traditional method uses a frequency modulation (“FM”) technique to modulate a low frequency sinusoidal signal onto a carrier frequency sinusoidal signal, which in turn triggers a pulse generator. In this method, most of the jitter parameters cannot be controlled, such as jitter distribution, jitter amplitude and the like. Thus, the system's jitter tolerance characteristics cannot be evaluated completely and accurately.
For instance, in phase locked loop (“PLL”) testing, the transfer function and input jitter caused output jitter cannot be easily determined. Similarly, in high-speed transceiver and A/D converter testing, jitter tolerance cannot be completely tested. Accordingly, what is needed is a controllable jitter generation technique to overcome these and other drawbacks and disadvantages of the prior art.